New Delhi, India

Available tracks and sessions

Maximizing Front-end Design: From ESL through RTL

• Meeting Your Complex SoC and System Design Goals on Time using ESL Methods Show abstract
  The need to design, integrate and verify multi-domain applications with ever growing software content into multi-core architectures, while meeting power, performance and quality of results requirements, is severely affecting project cost and design productivity. When designing cost-sensitive, high-performance and low-power products in competitive markets, missing any of these goals can be fatal. These challenges are at the heart of the Electronics System Level (ESL) promise by delivering a predictable and productive design process. This session will cover ESL architectural exploration, hardware virtualization, high level synthesis, and ESL links to RTL verification.
• 10x Verification Productivity Gains? What’s Practical and What Isn’t Show abstract
  Many challenges confronting design teams at the functional verification stage are inhibiting the advancement to a 10x increase in verification productivity. It’s obvious that we can’t just brute force the problem by throwing more compute resources at it. Challenges addressed in the session include:

  • Reaching 70-80% coverage is straight-forward using automated constrained random test methods. How can I reduce the time to achieve high levels of coverage and then quickly close the remaining coverage holes?
  • Systems include software as well as hardware. Simulation is impractical for validating anything longer than a 10’s or 100’s of lines of software code. How can I speed up the process of verifying my systems?
  • Systems include analog blocks within a majority digital SoC. How can I verify mixed signal functionality without dragging the verification efficiency to the level of a SPICE simulation?
  • Debug brings humans in the verification loop creating a huge drag on productivity. How can I speed up the debug process?
• A Methodology to Maximize Your AMS SoC Design and Verification Flow Show abstract
  The design and verification of the analog and mixed-signal functionality in advanced devices is a challenging task. High levels of integration and short time-to-market windows demand a well-planned and organized methodology. Mentor Graphics has developed the key technologies under its mixed-signal design and verification platform to facilitate such a methodology. The platform allows transparent and efficient combinations of analog/RF descriptions, AMS behavioral models and pure digital descriptions. System-level languages and fast-SPICE technologies are also fully embedded into the platform to complement this most flexible platform.
• ARM Fast Models – Accelerating Time to Market Presented by ARM Show abstract
  Virtual Platforms provide a solution for software development in the absence of hardware. ARM Fast Models offer a high-quality programmer’s view to the market - inside and outside of OSCI System-C and TLM-2.0 compliant EDA environments.

Accelerate Time to Manufacturing

• Minimizing Time to Tapeout With Signoff in the Implementation Loop Show abstract
  As mainstream ICs move down to 45nm and below, ensuring high manufacturing yield requires optimization and verification that goes beyond traditional timing closure and design rule checking. Considering signoff-quality DRC and design-for-manufacturing (DFM) checks after routing is too late because it causes large disruptions that require many ECO cycles to resolve. This session demonstrates how signoff-quality verification and model-based DFM can be included as part of a single interactive and highly-automated design closure flow by using Calibre directly during routing closure. With this approach, designers can ensure that they meet all signoff requirements at the same time they close their designs for timing, power, signal integrity and die size across all modes and corners of their operational specifications. Concurrent closure and signoff reduces time to market and uses engineering resources far more efficiently than traditional flows.
• Calibre Innovations to Reduce Your Signoff Cycle Time - Part #1 Show abstract
  This session provides designers with new tricks to beat the competition by speeding up their signoff process. The challenges of manufacturing at sizes below 45nm are driving much more complex design rule checks and model-based design-for-manufacturing (DFM) analysis before signoff. Other competitive demands, such as achieving signoff on IP from many suppliers, more stringent Design for Reliability (DFR) checks, and tighter error tolerances on extraction and simulation, are all adding to the difficulty and time required to complete signoff. This session will introduce attendees to a range of new innovations that simplify and accelerate the signoff process, including:

  • Equation-based DRC to speed DFM and other complex design rules
  • Programmable Electrical Rule Checking (ERC) to improve reliability
  • Auto-waivers to eliminate DRC violations that have already been waived by the foundry
  • High-performance 3D extraction with full-chip capacity and field solver accuracy
• Plug and Play Memory Test, Repair, and Programmability from RTL Planning Show abstract
  Embedded memory test must be thorough to avoid unacceptable DPM levels and often requires a repair method to improve yield. An incomplete memory test or new failure mechanism that escapes test can have a dramatic impact on a product’s profitability. This presentation describes a memory test flow that begins with test planning during RTL development to generate BIST circuitry that is easily, and automatically integrated into the design utilizing standard IEEE 1149.1 and 1500 test interfaces. The RTL insertion results in plug and play controllers which provide flexible field programmable test algorithms and built-in self repair methods. Furthermore, the standard interface supports 1st silicon debug and what-if testing utilizing a laptop communicating via USB to the TAP controller.
• Calibre Innovations to Reduce Your Signoff Cycle Time Part #2 Show abstract
  This session provides designers with new tricks to beat the competition by speeding up their signoff process. The challenges of manufacturing at sizes below 45nm are driving much more complex design rule checks and model-based design-for-manufacturing (DFM) analysis before signoff. Other competitive demands, such as achieving signoff on IP from many suppliers, more stringent Design for Reliability (DFR) checks, and tighter error tolerances on extraction and simulation, are all adding to the difficulty and time required to complete signoff. This session will introduce attendees to a range of new innovations that simplify and accelerate the signoff process, including:

  • Equation-based DRC to speed DFM and other complex design rules
  • Programmable Electrical Rule Checking (ERC) to improve reliability
  • Auto-waivers to eliminate DRC violations that have already been waived by the foundry
  • High-performance 3D extraction with full-chip capacity and field solver accuracy

Increase Productivity in System-level Design

• Designing in a World of High Speed and Power Show abstract
  The high speed/power content on a PCB continues to increase. In Mentor's 2009 Technology Leadership Awards program we had many designs entries with over 90% high speed constrained nets and more than 30 discrete power distribution networks. The high-speed constraints are a mix of classical buss interconnect, SERDES, and now DDR2/3 all requiring different types of rules and interconnect structures. This session will focus on the signal and power integrity best practice methods of designing your PCB for optimum performance.
• Design through Manufacturing - Getting your Product to Volume, on Time Show abstract
  No matter how productive you are in the PCB design process, you can lose all that advantage if your manufacturer can't get your product to target production volume on time.  Many of these issues can be addressed with high quality design-for-manufacturing (DFM) analysis functions that run concurrently with your design tools.  With Mentor's acquisition of Valor, users will benefit by having Valor's superior set of DFF and DFA checks integrated with the design process This session will speak to Valor’s DFA and DFF functionality in Mentor and non-Mentor PCB design solutions as well as enhanced capabilities to transfer your design data from you into manufacturing.
• Insanity! Using Your Existing FPGA Design Process & Expecting Improved Productivity Show abstract
  You’ve used your current FPGA design process time after time, project after project, yet your productivity does not improve. On the contrary, the process is slowing down your productivity as your FPGA projects get more complex. By taking a design approach that is requirements driven and well integrated from design creation through implementation, the project efficiency, productivity, predictability and final FPGA quality will dramatically improve. This approach will provide status and project visibility at every stage of the flow and deliver synthesis results that quickly meet design goals, keeping your projects on schedule. This session will walk through this approach and highlight the many new features in tracking, creation and FPGA synthesis that address the growing complexity and tackle the slowing design process. Enhanced tool integrations, improved design quality and reuse, and new industry-specific capabilities are some of the capabilities discussed that will enable you to deliver your FPGA projects on schedule, with the confidence that the FPGA is fully implemented according to spec and fully validated.
• Recommended Best Practices for Successful FPGA Design Show abstract
  The presentation covers the complete FPGA design flow from the basics to advanced design techniques. This methodology is FPGA vendor independent. The topics and recommendations are good practices that apply to any designs targeting FPGAs from any FPGA vendor. While most of the material is generic, it does refer to features in the Altera design tools that reinforce the recommended best practices. The diagram shown in figure 1, shows the outline of the best practices design methodology.

Embedded Symposium: Innovations in Embedded SW & User Interface Development

• How to Quickly Invigorate Your Device Utilizing 3D User Interface Technology Show abstract
  LCD displays and touch screens are now being applied to a broad range of embedded products, from remote controls to refrigerators. In today’s competitive consumer markets, such products may succeed or fail on the strength of their graphical user interface: visual appeal and “out-of-box” usability are critical. But getting the GUI right – and doing it on budget and on time – presents a major challenge to developers, since major changes to the GUI generally demand significant code modifications which add risk. This session will demonstrate how to eliminate this problem, enabling users to create, test and deploy radically different GUI designs without any modification to the underlying code. Advanced 3D effects and animation will be featured, even on low-end hardware, to quickly bring your product GUIs to life.
• Accelerating Embedded Systems with Android, Linux and Real-time Development Show abstract
  Android is an open source platform built by Google that includes an operating system, middleware and applications for the development of devices employing cellular communications. This session takes a look at the design of Android, how it works and how it may be deployed to accelerate the development of a connected device. Along with guidelines to getting started with Android, the Android SDK, its available tools and resources will be reviewed and consideration given to applications for Android beyond conventional mobile handsets such as medical devices, consumer electronics and military/aerospace systems. A brief review of how Android or Linux can co-exist with an RTOS in multi-core designs will also be conducted.