EDA Tech Forum

Companies are faced with an increasingly demanding and challenging global environment. To be competitive, your business must continuously improve productivity, lower costs, compress delivery times and enhance the quality of products, but how? This session will describe HDL design approaches to help reduce the design time to bring new and better products to market while improving quality with tighter integration and collaboration across the design flow and organization.

- Monitor development and milestones with requirements tracking to increase visibility into the project status for timely program and project decision-making
- Establish links between various design and verification processes to drive and monitor measurable results
- Enhance the collaborative design environment by providing a means for virtual real-time access to data and information
- Leverage IP to accelerate the development and verification of the design project
- Utilize advanced FPGA synthesis methods for optimal implementation

Transaction level models offer substantial value for system level purposes, such as virtual prototyping or architectural performance analysis. Those TLM models can then be used at the RTL design flow making excellent verification reference models. The popular verification methodologies being followed today, including OVM, AVM and VMM, all rely on a behavioral executable model of the device to be developed using standard languages such as SystemC and SystemVerilog. In this session we will learn how a scalable TLM methodology is used for all the TLM design tasks and how they deliver a connection between the early architectural model and implementation. This approach ensures that the transaction level model remains in sync with the implementation model, benefiting the architectural teams, the software/firmware integration team and the RTL implementation and verification team

The rise in capabilities in mobile consumer devices is driving a dramatic increase in the number and performance of application, graphics and signal processors integrated in System-On-Chip (SoC) designs. Each processor has specific system level requirements, such as low latency for the application processor or high bandwidth for the graphics, that need to be met by the on-chip digital highway to memory. To meet these performance needs while minimizing power consumption and silicon area, the design of the on-chip digital highway has become one of the most critical tasks of a SoC development. In this session, the speaker will discuss forthcoming design requirements for SoC devices in products such as ARM based Mobile Internet Device and smartphones and highlight how SoC architects, design and verification engineers can leverage ARM AMBA® protocol-based Fabric IP and design & verification tools to deliver highly differentiated SoC designs while minimising risks and easing the development task.

Hardware for mobile devices has some of the most intricate design constraints of any ASIC development flow. The hardware runs at relatively slow performance, but is constrained by tight area and power requirements. Design cycles are often less than a year, requiring tradeoffs to be made quickly without exploring all the possible solutions. Hidden away in most of the mobile devices manufactured this year you’ll find hardware built using high-level synthesis (HLS.) Usually it is focused on the wireless modem, and sometimes in the custom hardware for video and audio processing. We will discuss how HLS has been used successfully in mobile devices based on real-world experience. This will include best practices and the key technologies that make HLS a reality in mobile device design.

Many electronic designs are developed from system-level models of algorithms in MATLAB or Simulink. A highly effective verification methodology involves using these models as executable system specifications for implementation in FPGAs, ASICs, and SoCs. This session will demonstrate how to reduce verification time and verify implementations earlier in the design process. Links to simulators such as ModelSim, Questa and ADVance MS enable reuse of algorithm and system models to interactively test, verify, and debug hardware component designs. HDL code generation from MATLAB and Simulink can be used to create rapid prototypes of designs, accelerating testing in the target environment and enabling early identification and correction of target-specific errors. Directly generating test benches and simulation data for design debug and stand-alone verification reduces the effort needed for writing tests and managing stimulus and response data files. Learn how these methods have helped companies reduce verification times by 50 percent to 90 percent.

The high-performance, low-power SoCs at the heart of the multi-function electronics products of today’s wirelessly connected world pose specific verification challenges. Larger, more complex SoCs need to be verified in less time, and, because of the increasing dependency of the consumers on these products, the bar on quality is continuingly being raised as well. A highly effective functional verification strategy therefore is an absolute prerequisite for success, and this is exactly what this session addresses. We show how, based on a consistent methodology that maximizes reuse, multiple technologies, each focusing on a specific verification challenge, are orchestrated into a comprehensive solution that delivers the productivity to meet the design cycle and quality requirements while simultaneously providing the tools that enable you to execute a robust metric-driven verification process.

With the time to market pressures of today’s high-performance, low-power SoCs the multi-dimensional nature of the verification process the need for complete visibility is essential. Project managers are faced with the requirements of more functionality with equal or less resources, increased quality and all done sooner than the last project. Verification Management has become one of the most important factors in the verification process, the need to understand the impacts of resource and schedule upon the project has a major affect on the overall quality of the desired functionality. Too much time and resource are often taken up in the managing of the verification process instead of finding and fixing bugs. We show that having electronic closure between the test specification and design implementation allows any decision made in the dynamic development process easier to quantify the risks and achieve the highest quality goals.

Today's mobile devices are loaded with mixed-signal functionality. With arrays of transceivers for communication/connectivity, high-definition LCD and sensing devices for smooth and efficient user interfaces, high-fidelity A/V output for high quality music and video, sophisticated power management for long lasting battery life, and functions such as camera and audio recording, it’s obvious the analog and mixed-signal functions truly define the heart and soul of advanced mobile devices. The verification of the analog and mixed-signal functionality in advanced mobile devices is a challenging task. High levels of integration and short time-to-market windows demand a well-planned and organized methodology. Mentor Graphics has developed the key technologies under its mixed-signal verification platform, Questa ADMS, to facilitate such a methodology. The platform allows transparent and efficient combinations of analog/RF descriptions, AMS behavioral models and pure digital descriptions. System-level languages and fast-SPICE technologies are also fully embedded into the platform to complement this most flexible platform. Avoid silicon re-spins - learn how Questa ADMS can help you comprehensively verify your mixed-signal circuits in your mobile devices.

While the fabless-foundry IC development model has many advantages, one area where it can be challenging is in maintaining competitive differentiation. There are several factors which combine to limit differentiation of today’s mobile designs—increasing standardization of functions and protocols, greater use of outsourced IP, the consolidation of the foundry business, and increasing use of generic design rules and manufacturing processes. While these trends help reduce cost, they also make it difficult to gain a competitive edge and maintain margins, a phenomenon not unlike the evolution of the PC industry. While system design and functionality will always be keys to uniqueness, designers of leading-edge mobile ICs also need to consider a variety of ways to make their design more competitive at the implementation level. These opportunities include:

• System-in-Package (SiP) and Through-Silicon-Via (TSV) integration techniques to reduce size and improve performance
• Multi-corner, Multi-mode layout and Design-for-Manufacturing optimizations to reduce guard bands and increase performance and yield
• Electrical Rule Checking (ERC) to improve reliability through electrostatic discharge (ESD) protection and other circuit techniques
• Equation-based DRC to improve leakage and other operational characteristics
• Use of advanced design rule environments to capture best-known-methods (BKMs) for analog and mixed signal designs

Shrinking market windows, increasing development costs/complexity and the introduction of new innovative technologies such as high-k metal gate (HKMG) are accelerating the need for effective and practical DFM solutions. As technology advances below 65nm, key challenges facing both device manufacturers and designers will include not only the PPA (power/performance/area) targets but also yield robustness. This session will present an overview of the DFM solutions used by the Common Platform technology partners – Chartered, IBM and Samsung - in collaboration with our DFM ecosystem partners and key customers. These solutions are comprised of a combination of effective rules- and model-based tools, including those from Mentor Graphics, which enable the designers to make more informed tradeoff decisions with respect to manufacturability. Find out more details about the practical DFM approaches offered through Common Platform technology at IP and full-chip levels for 65nm/45nm with some early previews for 32nm.

As mainstream ICs move down to UDSM technologies (45nm and below), ensuring high manufacturing yield requires optimization and verification that goes beyond traditional timing closure and DRC check. One of the most important requirements today is achieving “power and SI closure” with multi-mode multi-corner considerations. Traditional low-power design techniques such as clock gating and mixed-Vt optimization are no longer adequate. Additionally, increasing interconnect resistance and variation in resistance is creating new implementation challenges due to its impact on circuit performance and reliability of clock trees. In this informative session, you will learn how to manage power throughout the implementation flow to improve productivity, reduce risk, and achieve optimal trade-offs among timing, power, SI, and area. Learn how engines such as placement, CTS and routing need to optimize for increased resistance and large variation of resistance across different process corners by optimally trading-off circuit performance, power consumption, SI, and die size. Architectural support for advanced multi-vdd methodologies including level shifter, isolation cell handling and multi-corner CTS will also be introduced.

ICs being developed at advanced technology nodes of 65 nanometers and below exhibit an increasing sensitivity to small manufacturing variations, as well as new failure mechanisms that previously were not commonly seen. As a result, systematic issues look like random defects to traditional analysis techniques. This causes failure analysis engineers to inspect a larger number of failed die to isolate and understand the underlying root cause. As a result, IC designers and manufacturers are seeing lower initial yields and slower yield ramps. Diagnosis driven yield analysis enables IC designers and manufacturers to leverage manufacturing test to effectively and accurately explain the cause of observable yield loss and make hidden yield limiters observable. Layout-aware diagnosis techniques determine the physical location and type of defects causing test failures. Statistical analysis of diagnosis results can then in turn be used to identify systematic issues and select which die that should be selected for failure analysis. This session will survey the biggest challenges in nanometer IC yield analysis and describe solutions that will be crucial to both IC designers and foundries.

With today’s high performance, high density, and high pin-count ICs, power delivery system design requires tight collaboration between the engineer and layout designer to ensure that clean, sufficient power is delivered to the ICs through multiple PCB power and ground structures. This session will focus on design and validation of board-level power distribution networks leveraging the new HyperLynx Power Integrity solution, enabling teams to reduce design cycle times, prototype re-spins and product cost, while improving system performance and reliability.

For complex, mixed technology system designs with RF, analog, and digital technologies, the RF portion commonly takes up to 75% of the total design cycle. At the same time, today’s RF systems have increased in complexity to a point where these cycle times are measured in months rather than weeks or days. Plus, design re-spins are common. The PCB design community has lived with these issues for a long time and the situation increasingly worsens as the most industries boost RF content in their products. This session will present innovative tools and methodologies to dramatically cut the design time, improve product performance, and lead to better quality PCBs containing mixed technology, including RF circuits.

With the complexity of FPGAs approaching that of ASICs and SoCs, FPGA designers need to focus on productive flows to meet time to market. This session will discuss the latest synthesis technologies as part of an integrated, predictive, vendor-neutral design environment. Attendees will be introduced to tools and methodologies that promote productive design creation and re-use, advanced synthesis, verification, and PCB integration.