EDA Tech Forum

Get the most out of your EDA Tech Forum experience by customizing your event schedule to focus on the areas of most interest to you. In both morning and afternoon sessions, you’ll gain valuable, in-depth technical knowledge of products, trends and issues that affect your daily work. You can choose one particular track or select sessions from various tracks, but either way, pre-registration is required.

Design for Low Power and High Performance

Track 1: Low Power - ESL to RTL

Optimizing for lower power earlier in the design cycle can have the greatest impact on low power performance. This track will look at emerging technologies for power optimization from ESL to RTL.

Track 2: Low Power - RTL to FAB

Meeting aggressive lower power goals demands careful attention from RTL through the physical design to fab. Advanced verification strategies as well as the new capabilities in place and route will be discussed in this track.

Track 3: High Performance Systems Design

Learn about the latest techniques for cutting edge systems design--from advanced fabrication to design for PCB power integrity.

Track 4: Achieving Yield for High Performance and Low Power

Design for Yield is becoming a critical competitive advantage with today's tighter market windows and higher manufacturing costs. This track will cover the newest in design solutions targeted at promoting yields while meeting low power objectives.