Greg Aldrich of Mentor Graphics outlines a yield-friendly diagnostic flow for the more detailed analysis of manufacturing defects.
Greg Aldrich is the director of marketing for the Design-for-Test (DFT) product group at Mentor Graphics. Prior to joining Mentor, Aldrich served as an applications engineer at Sunrise Test Systems in San Jose, California. He holds a bachelor’s degree in Electrical Engineering from the University of Illinois.
Nanometer scaling severely inhibits the path to achieve sustainable yield. In response more responsibility for forecasting potential failures must shift to design for manufacturing (DFM) methodologies that can be applied early in the design process. Yet, while these hold much promise, manufacturing test and failure analysis remains at the forefront of determining why chips fail.
Indeed, those chips that fail production offer a goldmine of information, which can provide valuable insight into defects and failure mechanisms. Developing a methodology that enables diagnosis of more than small samples of failing devices can thus greatly improve yield learning.
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