EDA Tech Forum Journal—the premier EDA publicationEDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends. |
Leakage power optimization for a wireless comms SoC
The article describes the implementation of the Blaze MO tool suite and results achieved with a first time user of the software.
Leakage has become a critical concern for sub-100nm silicon process technologies. It had started to become a significant factor in a chip’s overall power profile at 130nm, but by 90nm things had worsened with leakage accounting for perhaps 30% of a chip’s total power consumption. At 65nm, leakage represents more than 50% of power consumption. Similarly, the dynamics of yield have changed. Before the 100nm threshold was crossed, defect-related failures accounted for the majority of chip failures. However, at 65nm, parametric failures – i.e., chips that fail to meet power and timing specifications – have become dominant. Because of these recent developments, chip designers at both integrated device manufacturers and fabless semiconductor companies are searching for new ways to control leakage power and leakage variability, and to substantially increase parametric yield. This article shows how Blaze has been working with one semiconductor company to address the issue of leakage power. To view the rest of the article, login or register below New users, register to access all online articles and archives:To register for access to online articles and archives, simply fill out the fields below. Fields marked with
 are required. |
Puneet Gupta is a co-founder and Product Architect at Blaze DFM. He received his BTech degree in electrical engineering from Indian Institute of Technology, New Delhi in 2000 and an MS in electrical and computer engineering from UCSD in 2003.
David Parre is a senior applications engineer at Blaze DFM. He previously held engineering positions at Cadence Design Systems focusing on RTL-to-GDSII closure. Parre holds a Masters in electronics and computer science from ICPI-CPE Lyon, France.