EDA Tech Forum Journal—the premier EDA publicationEDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends. |
EDA Tech Forum Journal - December, 2007
volume 4, issue 4Inside:
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<Tech Forum>ESL/SystemC Using a 'divide and conquer' approach to system verificationJohn Willoughby of Carbon Design Systems outlines how to break down a tricky design task to deepen analysis of both hardware and software. Verified RTL to gates Asynchronous clocks prove tough for verificationRindert Schutten of Mentor Graphics highlights a need for tools that let engineers properly model metastability in a growing number of designs. Verified RTL to gates Visibility enhancement eases system validation for multicore SoCsMike Dickman of P.A. Semi and George Bakewell of Novas Software show how the PWRficient SoC met performance targets despite challenges during late-stage verification and system validation. Verified RTL to gates A verification methodology for programmable and reconfigurable processorsSven Altmann and René Beckert of the Fraunhofer Institute for Integrated Circuits detail new innovations in functional verification from the German research organization. Digital/analog implementation The simulation and design of software-defined radiosGreg Jue and David Leiss of Agilent Technologies provide case study insights into the deployment of this rapidly emerging technology. Design to silicon Portable multimedia SoC design: a global challengeA team from the application processor division of STMicroelectronics walk us through the development of the most recent Nomadik system-on-chip. <Commentary>Analysis Start HereDespite economic worries, there is an excess of venture capital funding looking for a home. The cutting edge UPF delivers on powerYatin Trivedi of Magma Design Automation describes how one EDA alliance is driving a new power format to standardization. Memory Focus - Analysis Mastering the memory mazeLane Mason and Marc Greenberg of Denali Software act as our guides through some delicate choices for consumer designers. Memory Focus - Tested component to system Implementing DDR3 DIMMs with modern FPGAsSalman Jiva of Altera explains how the incoming memory standard can be deployed in a programmable logic environment. |
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