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Asynchronous clocks prove tough for verification

For simulation to correctly predict silicon behavior, the logic implementing a design should adhere to the setup and hold constraints specified for clocked elements. However, with multiple asynchronous clocks on a single chip driving logic, designers cannot help but violate setup and hold constraints. This causes metastability, which in its turn leads to non-deterministic delays through synchronizers. For these types of designs it is critical that a designer has the tools to accurately simulate these non-deterministic effects while performing their functional verification.

Therefore, for designs that have asynchronous clocks, the traditional verification flow should be augmented with a comprehensive clock-domain crossing (CDC) verification solution that addresses the following:

  1. The complete identification of all clocks, CDC signals, verifying whether correct synchronizers are in place.
  2. The designer's ability to verify whether the design correctly implements the CDC protocols that ensure uncorrupted data transfer between clock domains.
  3. The means to augment the simulation with behavioral metastability models (BMMs) to account for the non-determinism introduced by metastability and thereby accurately model silicon behavior.

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