EDA Tech Forum

While DDR3 SDRAM offers speed and low-power benefits, the fly-by termination topology defined by the JEDEC specification for DDR3 SDRAM DIMMs creates interesting challenges for FPGAs. The JEDEC topology significantly reduces the simultaneous switching noise that plagues high-frequency parallel interfaces, but also introduces the need for read and write leveling to compensate for the deliberate skew found in the DQ data path.

This article looks at how high-end FPGA I/O cells interface to DDR3 SDRAM to take advantage of these speed and power benefits. It examines how leveling is achieved in the FPGA for operation with a DDR3 SDRAM DIMM; how to use dynamic on-chip termination to alter the impedance on a bidirectional bus and save power; and how to use I/O delay for de-skew within a DQS group.

It also discusses how intellectual property (IP) control algorithms are used in the PHY data path to calibrate the read path at start up and compensate for voltage and temperature variations during operation, enabling the design to reach the highest levels of reliable operation over PVT.