A verification methodology for programmable and reconfigurable processors(intro)

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Home > Journal > December, 2007

A verification methodology for programmable and reconfigurable processors

The article describes and illustrates, by way of a case study, an innovative approach to functional verification. It enables the reuse of test patterns through the coordinated combination of a top-level testbench and subordinate testbench modules. It is based on a new add-on tool, VTrac+, that extends Mentor Graphics’ ModelSim/Questa software to stimulate, compare and trace signals. The add-on is used for pattern transfer inside hierarchical testbenches; the automated evaluation of hundreds of thousands of patterns in regression test suites; and the injection of test patterns generated by third-party tools.

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