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Visibility enhancement eases system validation for multicore SoCs

How visibility-enhanced debug works

The emergence of ‘visibility enhancement’ technology provides verification teams with an optimal trade-off between simulation performance and signal visibility. Visibility enhancement enables a methodology consisting of an analysis-driven partial signal dumping procedure that limits the impact on emulation performance while still providing full signal visibility for debug. These are some key components:

  • Visibility analysis analyzes RTL and netlist representations to determine the minimum set of essential signals required for full visibility. This provides the flexibility needed to target an entire design or only those blocks and signals of interest.
  • Data expansion automatically computes missing signal data that is based on essential signal data and design knowledge provided by the RTL or the netlist. The data regeneration process is optimized by computing ‘on-demand’ only those values required for debug.
  • Abstraction correlation automatically maps gate-level verification results to RTL design descriptions. This interoperates seamlessly with the data expansion engine to enable analysis and debug with full visibility into the RTL design

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