EDA Tech Forum Journal—the premier EDA publicationEDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends. |
Tightening the loop on coverage closure
|
The article describes how methodologies such as graph-based intelligent testbench automation will help engineers efficiently create verification scenarios and stimuli. This is a powerful way of enhancing advanced verification environments and reducing common verification headaches (e.g., reaching coverage goals). Such strategies can help to free up resources, in terms of time, people and hardware, so that the design team can focus on the challenges of realizing a more ambitious verification plan and of creating better functional coverage metrics. This enables the verification team to ensure that the device has been exercised in a far more comprehensive manner, thereby reducing the resulting defect density. The article considers some broadly applicable approaches with specific reference to Mentor Graphics’ inFact tool. This has new algorithms to improve coverage and has been optimized for the use of multi-machine simulation farms to linearly improve simulation runtimes. To view the rest of the article, login or register below New users, register to access all online articles and archives:To register for access to online articles and archives, simply fill out the fields below. Fields marked with
 are required. |