EDA Tech Forum

System-in-package (SiP) used to be thought of as a ‘poor man’s system-on-chip’ (SoC). Not any more. The complexity involved in implementing various levels of functionality on a single SoC is reaching such levels that it is becoming increasingly difficult to justify the design and manufacturing costs. Similarly, the need to deliver products within equally tight (and sometimes tighter) time budgets means that the reuse of intellectual property and proven blocks, where possible, is highly desirable. Certainly, no one wants to re-invent the wheel.

SiP itself is beginning to offer a number of techniques that provide SoC-like levels of integration and meet demands from performance through to form factor. Such techniques include stacked die and through-silicon vias. Although talked about for some time, they are only now beginning to become more widely available from semiconductor foundries.

This special article takes the form of an interview with Tom Quan, deputy director of design services marketing at TSMC, the world’s largest foundry. The company included SiP in its Reference Flow 10, launched at this year’s Design Automation Conference. Quan discusses TSMC’s views on SiP’s market position, tools for its realization and the technical challenges, among other issues.