EDA Tech Forum Journal—the premier EDA publicationEDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends. |
June, 2005
volume 2, issue 2Inside:
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<Tech Forum>ESL/SystemMicro-architecture exploration for deep submicron designAlcatel Space’s Louis Baguena describes how synthesizing directly from C cut design cycle times. Verified RTL to gatesFormal verification poised for rapid growthPranav Ashar and Rich Faris of Real Intent explain how static assertion-based verification is entering the mainstream. Digital/analog implementationImproving team productivity with efficient data management for SoC designsScott Humphreys of RF Micro Devices and Srinath Anantharaman of ClioSoft outline how you can use DM to smooth the design flow. Design to siliconAchieving better DFM: EDA tools pave the way to improved yieldMentor Graphics’ Joseph Sawicki sets out how EDA tools are aligning the traditional world of design rules with design for manufacture. Design to siliconA methodology of integrated post tape-out flow for fast design to mask TATSMIC’s Chi-Yuan Hung explains how the foundry secured a 5X improvement in turn-around-time. Tested component to systemPower analysis for efficient power planningMouzam Kahn of Altera highlights the importance of power analysis in PCB design. <Commentary>Destination network-on-chipA University of British Columbia team outlines some of its research results on the progression from SoC to NoC. Moore's LawThe whole pictureSiGe pioneer and DAC keynoter Bernard Meyerson says Moore’s Law has been misunderstood and that a new, holistic approach to design is needed to overcome the discontinuity. Innovate in volumeAnd it isn’t easy, even for Texas Instruments, as Hans Stork, its CTO, explains. The ultimate wish-listThe clearest indicator of what engineers want from EDA is the annual DAC line-up. What does this month’s conference highlight as 2005’s priorities. SystemVerilogSystemVerilog is changing everythingAccellera secretary Karen Bartleson outlines the benefits of the first hardware design and verification language. |
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