Accellera’s Karen Bartleson charts the design language’s genesis and emerging benefits as it moves rapidly to becoming an IEEE standard
Karen Bartleson is director of interoperability at Synopsys and secretary of the Accellera standards organization.
Considering how complexity has grown over the last 20 years, it is amazing how few dramatic shifts in the design and verification methodology have occurred. When they do happen — mylar to layout tools, gates to RTL, hand-crafted test vectors to testbench automation — they make our work as engineers easier and enable us to tackle more challenging projects.
Today, we are undergoing another such dramatic shift, one enabled by the SystemVerilog language. It was developed through Accellera’s standardization process and is rapidly approaching ratification by the IEEE as the P1800 standard.
SystemVerilog is changing everything — design, verification, architectural modeling, the EDA industry, even the way standards are developed — and for the better.
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