EDA Tech Forum Journal—the premier EDA publicationEDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends. |
EDA Tech Forum - June, 2006
volume 3, issue 2Inside:
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<Tech Forum>ESL/System CTechniques for low power at the system levelGeorge Harper of Bluespec analyzes emerging approaches to tackling the power crisis at higher levels of abstraction. Verified RTL to gatesA SystemVerilog AMBA ABP monitorDarko Vukicevic of HDL Design House describes a recent assertion-based verification project undertaken by his company. Verified RTL to gatesAddressing the design closure crisisDimitris Fotakis of Athena Design Systems argues that new approaches to computation could alleviate today’s persistent closure problems. Digital/analog implementationDeploying the right tools for mixed signal verificationGeoffrey Ying of Synopsys illustrates how to deal with this critical design phase based on a VoIP WLAN system on chip case study. Design to siliconDesign and manufacturing unite to tackle process variabilityJean-Marie Brunet of Mentor Graphics shows how the Litho-friendly Design concept can help designers cope with the impending 65nm process node. Design to siliconHigh quality yield modeling is critical for DFMJoseph Davis and Patrick McNamara of PDF Solutions highlight the importance of coordinating and calibrating different yield techniques as geometries shrink. Tested component to systemAccelerating the move from prototype to production with a robust design flowRo Chawla of Altera describes how the chip company’s tools smooth the transistion from FPGA to structured ASIC. <Commentary>Powering the third digital electronics revolutionAnalyst Malcolm Penn surveys the design priorities highlighted by the reality of ubiquitous electronics. New dimensions in performanceIBM’s Kerry Bernstein was a skeptic when he first started working on 3D chip architectures. Now, he’s an evangelist. Of a common mindThe EDA Consortium exists to do what no tool vendor, even the biggest, can do on its own. Chairman Wally Rhines discusses its 21st century agenda. Back on the bayThe 2006 Design Automation Conference returns to San Francisco for the first time since 1998.We review the trends and program content with general chair Ellen Sentovich. I hate to say this but...Cadence founder Joe Costello has the dual perspective of being an EDA pioneer and now a player in consumer electronics. |
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