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Techniques for low power at the system level

This article outlines key factors in designing for low power and energy based on system-level strategies and techniques and highlights how ESL synthesis facilitates and automates automates many of the tasks involved.

undefinedGeorge Harper is vice president of marketing at Bluespec and has more than 15 years of experience in the semiconductor industry. He holds a BSEE and a MSEE in Electrical Engineering from Stanford University, and an MBA from Harvard University.

Designers thinking about low power and energy have a variety of strategies at their disposal. The most common are:

  • Process/libraries (e.g. low-power processes/libraries; high and low threshold voltage cells; and voltage scaling);
  • Power and voltage domains;
  • Clock gating;
  • Low-power optimized clock synthesis;
  • Low-power synthesis (e.g. automatic insertion of operand isolation circuitry);
  • Implementation optimizations (e.g. operand isolation; pre-computation; and power efficient scheduling of resources).

So, with such a plethora low power tools and capabilities focused on post-register-transfer level (RTL) stages in the design flow, why should you bother with or care about what electronic system level (ESL) synthesis can do for power? A huge part of the answer is that architectural tradeoffs can have a 10X bigger impact than decisions taken further downstream in the design flow, and ESL synthesis, in turn, provides the best vantage point for making – and, thereby, optimal control over – these kinds of architectural, micro-architectural and implementation choices that drive energy consumption.

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