EDA Tech Forum

Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing number of operational modes and process corners in which a design must operate is exacerbating the problem and significantly increasing the time needed to reach design closure.

To properly address SI closure for ICs manufactured at 65nm and below, we need to take SI into account throughout the design flow. It must be on the agenda from the start of placement, and stay on it through clock tree synthesis, optimization and routing. We must be equipped to undertake accurate analysis, and to apply effective prevention and design optimization techniques at all appropriate stages.

Additionally, we need the ability to perform concurrent SI analysis and optimization for all operational modes and process corners. This requires a new place-and-route architecture that has an underlying ability to carry out multi-corner multi-mode (MCMM) timing analysis. Solutions without true MCMM capability can only present a single mode/corner combination for SI analysis at any one time, forcing design teams to run multiple time-consuming iterations of the tool and also to intervene manually in the process.