EDA Tech Forum Journal—the premier EDA publicationEDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends. |
EDA Tech Forum, March, 2007
volume 4, issue 1Inside:
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<Tech Forum>ESL/SystemC Electronic system level design for embedded systemsJeff Roane of VaST Systems Technology addresses how best to model processors and exploit software virtual prototypes as embedded software plays an ever greater role. ESL/SystemC System-level design maturesChris Lennard & Seth Bernsen of ARM and Jeremy Bennett of Tenison Design Automation chart the progress made in bringing ESL to fruition for commercial chip development. Verified RTL to gates Revealing the hidden cost of performance for physical verificationJohn Ferguson of Mentor Graphics identifies the critical dollar factors often overlooked during a cost-benefit analysis of tools for this slice of the design flow. Digital/analog implementation Automating design for high volume consumer marketsKevin Steptoe of Pulsic describes a 'custom design automation' strategy that overcomes the problems ASIC-focused tools pose on silicon that undergoes multiple ECOs to enhance yield. Design to silicon Scan infrastructure and environment for enhanced at-speed ATPGStephen Pateras of LogicVision proposes a new methodology that aims to overcome the limitations of traditional and sequential ATPG for deep submicron designs. Design to silicon Confronting chip assembly challengesSudhakar Jilla of Sierra Design Automation sets out a new approach to addressing the impact of variation on assembly and avoiding late re-spins. Tested component to system Re-evaluating the flow for package-aware chip designJoel McGrath of Rio Design Automation explores the need for a more holistic and earlier focus on packaging in the era of SiP and other emerging integration strategies. <Commentary>Analysis Consumer market promises steady progressBut who is getting the benefit as the attack of ASPs continues? We review the latest CEA data. Interview From A to B via ZStanford professor and IEDM keynoter Tom Lee argues that technology has its foundations in the joy of human chaos. The Cutting Edge MPSoC demands system-level design automationCan the multiprocessor system-on-chip take us through impending road blocks? Peter Flake and Frank Schirrmeister of Imperas act as our navigators. Design Economics 'Build vs buy' in an SoC worldPhil Casini of Sonics addresses the economic case for adopting outsourced IP at the interconnect. Preview Double figures for DATEWe preview this spring’s Design Automation and Test in Europe conference in Nice, France. |
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