EDA Tech Forum

Design is at the edge of the power cliff. The multiprocessor system-on-chip can pull it back, say Peter Flake and Frank Schirrmeister.

The relative performance of a single processor has leveled off in the last decade. Built-in instruction-level parallelism is becoming less efficient because issuing more than four instructions in parallel has little effect on most applications. Meanwhile, recent attempts to boost performance have come dangerously close to the energy/power consumption ceiling. Dedicated hardware accelerators may prove valid alternatives for some applications, but do not offer the flexibility and programmability an expensive chip development project needs to meet time-to-market nor optimize its longevity. We need alternative solutions. One of the most promising is the multiprocessor-system-on-chip (MPSoC).

MPSoCs address power issues largely by exploiting parallel software. Multiple processors can execute at lower frequencies, resulting in comparable overall MIPS performance; designers can slow clock speed, a major constraint for low-power projects. However, MPSoC transfers challenges from hardware to software as traditional sequential software does not exploit parallelism.