EDA Tech Forum

There has been a recent trend for tools originally aimed at ASIC designs to be applied to the design of high-volume projects aimed at markets such as consumer electronics. The article argues that there are a number of fundamental flaws in such a strategy.

For example, an ASIC tool might be designed for an environment where yield is a one-off issue: once the device achieves a satisfactory yield, it is likely to remain the same until succeeded by a next generation product. By contrast, a flash design may undergo numerous engineering change orders (ECOs) during its lifetime as the supplier seeks to eek out as much profit as is possible by constantly addressing yield - perhaps even executing 10 mask revisions to secure just a 1% yield increase.

This gap in intentions points to the need for tools that support a Custom-Design Automation (CDA) strategy, more suited to a potentially constant flow of ECOs that underpin ongoing profitability for high volume silicon.

The article offers the Unity constraint-driven floorplanning, placement, routing and editing platform as an example of CDA and describes how it would be implemented as such.