EDA Tech Forum

Until recently, hierarchical design flows have been favored for the implementation of multi-million gate SOCs. However the rapid increases in design size brought on by nanometer process geometries have seen engineers seek to cope with the inherently block-based nature of such flows by seeking greater concurrency between the block implementation and chip assembly stages in the hierarchical structure.

Here, designers have faced limitations largely created by the tools available to them. The article identifies five areas in particular - abstraction-generated violations, bad budgets, bad pin assignements/block placements, clock tree synthesis limitations, and full-chip static timing analysis limitations – that lead to problems only becoming apparent late in a design project’s life, with serious implications for factors such as a successful design to specification and time-to-market.

In response, the article proposes a methodology based on a new generation of tools that addresses four aspects of chip assembly and associated flow steps - infrastructure enhancements, full-chip static timing analysis engines, chip closure optimization and chip-level clock tree synthesis – and puts more power to deal with variability and other factors into the hands of the designer.