EDA Tech Forum

Chip and package design are all too often still seen as separate stages in the design process. In today’s nanometer age and with the growing use of techniques such as system-in-package, this lack of integration can have catastrophic results. Package designers frequently encounter overly complex and un-routable silicon that requires multiple iterations to fix. Problems that occur so late in the design flow have an inevitable impact on both NREs and time-to-market.

The article describes an alternative methodology, ‘package-aware chip design’, that allows various I/O and related challenges to be addressed early in a project’s life with the goal of creating a one-pass flow. This methodology needs to be applied ideally during prototyping and certainly before floorplanning. The objective is give both chip and package engineers a clear view of the challenges that lie ahead.

Specific requirements for this methodology are discussed. The author explains why and how it enables a die to be designed within the context of the external environment, the package substrate and the PCB. He highlights the development of design constraints at the appropriate design stage to ensure the best placement of I/Os, associated logic, bumps and routing and the best interplay between various design disciplines.