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EDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends.

Scan infrastructure and environment for enhanced at-speed ATPG

Deep submicron system-on-chip designs are facing increasing yield fall-out issues. At 90nm, 30% of the problem can be attributed to performance and signal integrity issues whose detection requires efficient at-speed test and characterization. However traditional and more recently introduced sequential ATPG techniques have a variety of limitations. The article proposes a new BurstMode scan methodology that addresses these shortcomings based on integrating a hierarchical, atspeed single capture scan infrastructure into the design.The fundamental technology behind this methodology is described as is the process of inserting the new approach into a typical major project design flow.

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