EDA Tech Forum Journal—the premier EDA publicationEDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends. |
March, 2008
volume 5, issue 1Inside: Subscribe now for future issues.
<Tech Forum>ESL/SystemC ESL at the inflection pointMore mature system-level design techniques can now be used effectively on real-world projects, says Marc Serughetti of CoWare. Verified RTL to gates Parasitics: an old problem reaches new heightsProblems that most EEs first encountered as students are having a growing influence on sub-90nmdesign, according to GerhardAngst of Concept Engineering. Verified RTL to gates Active power management for configurable processorsBrian Knowles of ARC International describes how to gain a fourfold increase in power efficiency on battery-powered devices. Digital/analog implementation Efficient packet header parsing using an embedded configurable packet engineRama Mwikalo of Cswitch shows the power of his company’s new configurable communications processor in this case study. Design to silicon Towards an infrastructure for profitable DFMCommon models will help the industry achieve real efficiencies from design for manufacting, argues Jake Buurma of the Silicon Integration Initiative. Tested component to system High quality scan test with minimal pinsRon Press of Mentor Graphics illustrates how test engineers can get around pin limitations on current devices and still achieve the best results. <Commentary>Start here A question of freedomThe CEA believes free trade is at grave risk. You don’t have to agree. You do have to wonder. Analysis To pause and take stockOur annual review of the consumer electronics sector is short on compelling new products – but maybe that is not a bad thing. Design strategies How VHDL designers can exploit SystemVerilogThe emerging language can bring powerful verification features to more established design environments, explain Karen Pieper and Karen Bartleson of Accellera. Interview The veteran competitorWe discuss the future of the foundry model with its creator, TSMC chairman and CEO Morris Chang. Conference preview The European viewThe Design Automation and Test in Europe conference moves back to Germany and its regular place in the EDA calendar. |
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