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Efficient packet header parsing using an embedded

Cswitch’s CS90 Configurable Switch Array device has an interconnect structure, the dataCrossconnect network, that delivers bandwidth at 40- 100Gbps for packet-based applications. For packet handling tasks, the chip includes embedded configurable blocks, Configurable Packet Engines, that support functions such as frame parsing, CRC and hashing, and fast address look-ups, all at up to 1GHz. For storing packets, the chip includes over 18Mb of on-chip memory and support for the latest high-speed memories. All these elements are completely configurable. Additionally, the chip includes look-up table-based logic that supplements these blocks.

This article discusses the CSA’s capabilities in terms of complex packet inspection and processing, and the Packet Parser CPE incorporated within the CS90. These are illustrated through implementations for a Q-in-Q Layer-2 application and an Ethernet generic-framing procedure (GFP) application in a metro networking context.

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