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EDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends.

High quality scan test with minimal pins

Changes in defect distribution, increasing design complexity and pressures from the specialist I/O and packaging arenas are creating a dilemma during component test. On the one hand, the generation of more test patterns would appear to be necessary; but on the other, fewer test ports are available.

The article describes a strategy for addressing this tension by the appropriate augmentation of scan compression technologies with techniques that minimize the number of test interfaces required and enable reduced pin-count test (RPCT). These can meet demands for high-quality test without increasing cost or adding unacceptably to design times. The article also addresses how low pin-count test methods support modern design realities such as multi-site test and volume diagnostics.

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