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How VHDL designers can exploit SystemVerilog
The emerging standard’s powerful verification features are not limited to Verilog users, explain Karen Pieper and Karen Bartleson
Learn more about SystemVerilog at www.systemverilog.org. SystemVerilog, the standard that originated from Accellera and is now IEEE1800, is not just for Verilog users. VHDL users can also improve their design processes using its proven verification features. Anyone involved in systemon- chip (SoC) design may face a mixed-language environment and will appreciate being able to leverage SystemVerilog with the VHDL portions of their design. Many commercial simulators support mixed-language simulation, providing proven deployments at high performance by way of a native implementation of the features in the simulator. Some beneficial techniques include assertion-based verification, constrained random stimulus generation, and functional coverage tracking. These are available in SystemVerilog blocks and can be bound into VHDL designs without modification to the original RTL. To view the rest of the article, login or register below New users, register to access all online articles and archives:To register for access to online articles and archives, simply fill out the fields below. Fields marked with
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Karen Pieper is chair of the IEEE 1800 SystemVerilog working group and synthesis R&D director at Synopsys.
Karen Bartleson is treasurer of Accellera and director of interoperability at Synopsys.