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EDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends.

Parasitics: an old problem reaches new heights

The semiconductor industry faces increasing challenges in the design of complex systems-on-chip, and while some have sprung from new, only recently anticipated sources, others are, in fact, very familiar. Foremost among these are the interconnect delays caused by the increasing influence of parasitic networks. Parasitic inductance is also a growing concern.

The causes of parasitic effects are well understood, as they pull upon such fundamental concepts as resistance and capacitance and they function in very much the way of the RC network that EEs will have first encountered as students. However, how they are addressed at today’s level of complexity – particularly in cutting edge SoC designs – still raises many questions over methodology and how available tools should be deployed.

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