EDA Tech Forum Journal—the premier EDA publicationEDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends. |
EDA Tech Forum - September 2005
volume 2, issue 3Inside:
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<Tech Forum>ESL/System CThe automated generation of golden timing constraintsAjay Daga of Fishtail Design Automation explains how freezing timing requirements can reduce the closure process by up to eight weeks. Verified RTL to gatesVerifying micro-architectural optimizations for high-performance system-on-chip designsNarayanan Krishnamurthy of Qualcomm, and Calypto Design Systems’ Anmol Mathur and Mitch Dale show how a new technique can take the pain out of sequential checking. Digital/analog implementationThe new shape of layoutKevin Steptoe of Pulsic illustrates how shape-based routing has translated from board to chip design as an aid to meeting timeto- market. Design to siliconSub-90 nanometer variability is here to stay…deal with itPhilippe Hurat,Yao-Ting Wang and Nishath K.Verghese of Clear Shape Technologies highlight a growing need for design for variability. Design to siliconPCB structures and embedded componentsMentor Graphics’ Dean Wiltshire considers how embedded components can deliver better, denser and cheaper PCBs but also raise new design flow challenges. Tested component to systemThe need to unify design and test dataSergio Perez and Fred Bode of the Semiconductor Test Consortium discuss how a drive for open standards in ATE needs and aims to integrate with EDA. <Commentary>Market analysisMemory and storage for mobile electronicsLane Mason and Brian Gardner of Denali Software map developments in this often tricky area for consumer electronics design. RegulationOnly a WEEE beginningNew European electronics-recycling legislation will soon be followed by tighter restrictions on component materials. Paul Dempsey reports. Nano-electronicsJust do itHarvard nanoelectronics pioneer Charles Lieber says his discipline must get beyond the hype and show what it can do. Best of DACAn efficient algorithm for statistical minimization of total power under timing yield constraintsEDA Tech Forum publishes the first of the two ‘best of ’ papers from the 2005 Design Automation Conference. Murani Mani and Michael Orshansky of the University of Texas, Austin and Anirudh Devgan of Magma Design Automation discuss a new algorithm for power reduction. |
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