It is currently impossible to accurately predict IC design performance without modeling final on-chip transistor device shapes and process variations. However, for predictable silicon success below 90nm, these variations must be considered early in the design flow.
Dr. Philippe Hurat is Clear Shape’s senior marketing director. He holds a PhD in microelectronics from INPG, the National Polytechnic Institute of Grenoble, France, and an MS in computer science from the University of Joseph Fourier, Grenoble, France.
Dr. Yao-Ting Wang is CTO, chairman and co-founder of Clear Shape. He received his PhD and MS in electrical engineering from Stanford University, and his BS in electrical engineering from National Taiwan University.
Dr Nishath K. Verghese is vice president of engineering - design technology at Clear Shape. He holds a PhD and an MS in electrical and computer engineering from Carnegie Mellon University, and a BS in electrical engineering from Birla Institute of Technology and Science in India.
Timing, power and noise closure for sub-90nm IC designs face an unprecedented number of challenges due to variations introduced by lithography and copper/low-k interconnects. This raises the serious threat of low yields due to poor prediction of what will happen in silicon, followed by costly re-spins to debug and correct designs.
Existing rule-based design for manufacturing (DFM) tools and the attendant infrastructure are falling woefully short in accurately predicting silicon performance, power, and noise. Rule-based tools are unable to account for a design’s sensitivity to process, resolution enhancement technology (RET) and chemical mechanical planarization (CMP) variations.
Engineers need tools that provide a predictable early detection and correction of a design’s sensitivity to these factors — the earlier, the better. Such detection cannot be achieved without fundamental innovations in the following areas:
are required.