The design of high-performance silicon often requires microarchitectural changes to the RTL to achieve aggressive timing and power specifications.
Narayanan Krishnamurthy is a staff engineer in the ASIC Design Automation group at Qualcomm. He holds a BTech in Instrumentation from the Indian Institute of Technology, India and an MS and PhD in Electrical and Computer Engineering from the University of Texas at Austin.
Mitch Dale is director of product marketing for Calypto Design Systems and has more than 17 years of experience in functional verification marketing and engineering. He holds a BS in Applied Mathematics and Computer Science from UC Berkeley.
Anmol Mathur is chief architect and co-founder of Calypto Design Systems. He holds a BTech in Computer Science and Engineering from the Indian Institute of Technology, India. He also holds an MS and PhD in Computer Science from the University of Illinois at Urbana-Champaign.
Making design optimizations
Design teams expend tremendous effort trying to reach timing and power closure. It is not uncommon to spend weeks laboring over synthesis in a bid to remove one last failing critical path. To address this problem, engineers attempt to push RTL through synthesis as soon as is feasibly possible. Nevertheless, typically near tape out, full chip integration reveals challenging closure problems. At this point, designers need a way to make powerful sequential changes with the confidence that they are not breaking functionality.
Sequential changes, such as micro-architectural optimizations, cannot be verified by classic combinational equivalence checkers because the state elements in the two designs are not guaranteed to match. Sequential changes can also invalidate existing simulation testbenches due to temporal or latency differences at the outputs. Moreover, traditional simulation is limited by performance and functional coverage, adding yet another degree of uncertainty to the verification.
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