EDA Tech Forum Journal—the premier EDA publicationEDA Tech Forum journal is a quarterly publication for the Electronics Design Automation community including design engineers, engineering managers, industry executives, and academia. EDA Tech Forum journal provides an ongoing medium in which to discuss, debate, and communicate the electronic design automation industry’s most pressing issues, challenges, methodologies, problem-solving techniques, and trends. |
EDA Tech Forum - September, 2006
volume 3, issue 3Inside:
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<Tech Forum>ESL/SystemCNative SystemC Assertion mechanism with transaction and temporal assertion supportAtsushi Kasuya, Tesh Tesfaye and Eugene Zhang of Jeda Technologies explain how a new assertion engine eases the use of TLM in verification. Verified RTL to gatesVerifying complexity with an all-encompassing methodologyTom Fitzpatrick and Mark Glasser of Mentor Graphics address how engineers can leverage transaction-level modelling and other techniques for verification efficiencies. Verified RTL to gatesThe 'What', 'When', and 'How Much' of functional coveragePaul Marriott of Xtreme EDA explains how to approach this critical yet so easily botched part of the design flow. Digital/analog implementationA top-level verification methodology including power supply and signal check using mixed-signal simulationSilvia Strähle and Timo Gossmann of Infineon Technologies tackle expanding simulation times for mixed-signal SoCs. Digital/analog implementationCoverage-driven verification for the analog domainMonia Chiavacci and Gabriele Zarri of Yogitech offer their perspective on how to bring digital and analog verification into the same environment. Design to siliconVisibility enhancement for full-chip simulationYu-Chin Hsu of Novas Software shows how the technique can cut the cost of getting enough signal value information to debug complex problems. Design to siliconAdvanced post-silicon verification and debugHeinz Holzapfel and Peter Levin of DAFCA demonstrate how a debug infrastructure at the RTL can be reconfigured for post-silicon validation and debug. Tested component to systemEmbedded non-volatile configurable program storageCharles Ng of Kilopass Technology offers system designers an alternative route to incorporating program code storage for in-field upgrades. <Commentary>Lead-free but not problem freeThe EU's clampdown on lead and other hazardous materials is still a source of much confusion. Last of the PioneersWilf Corrigan may prove to be the last of Silicon Valley's original innovators to lead a major chip company. SPIRIT achieves maturity with IP-XACT specificationsThe consortium is undergoing some major changes. Chris Leonard and Ralph von Vignau provide an update on this closely watched initiative. |
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