EDA Tech Forum

The article describes a post-silicon validation and debug methodology based on the insertion of a debug infrastructure at the RTL level. It can then be dynamically reconfigured post-silicon to adapt to actual validation and debug situations.

More than 50% of highly complex systems-on-chip (SoCs) have functional issues at first silicon, issues that emerge after engineers have spent much time and money on verification and emulation. These issues delay time-to-ramp and cause significant losses of direct and indirect product revenue. All this demonstrates the need for efficient post-silicon debug methodologies and tools.

Post-silicon debug is a serious challenge. Only a few of the thousands of important internal signals are directly accessible and observable during normal chip operations. An important factor here is the limited number of pins of the SoC. A key objective of post-silicon verification and debug methodologies is to provide observability and control of as many internal signals as required, while keeping the area overhead and timing impact as low as possible.