EDA Tech Forum

The article addresses the development of a comprehensive verification environment in the era of transaction-level modeling. How can engineers utilize existing techniques and languages most effectively and efficiently?

The increased size and complexity of designs continues to push design and verification methodologies to progressively higher levels of abstraction. These upward shifts in abstraction tend to occur about every decade or so, and we are currently experiencing one in the shift from RTL to transaction-level modeling (TLM).

Abstractions must eventually be converted back effectively and efficiently? In its most basic sense, verification is the to detailed designs in order to be implemented. The most interesting aspect of the shift to TLM is that it is the first upward shift in modeling abstraction not accompanied by a corresponding, automated path back to the lower abstraction level. The RTL shift was accompanied by (and was largely caused by) the advent of synthesis. In contrast, as a design moves up to the transaction level, the transition down to RTL is essentially manual — although some tools can automate parts of the process.

The only way to ensure the integrity of the transition is to put together a verification environment that can effectively verify the design at multiple levels of abstraction. To do this, one needs a methodology that is targeted at solving the problem of how to verify designs consistently at those multiple levels. In addition, the methodology must make it easy for users to take advantage of functional coverage, constrained-random stimulus generation, assertions, and other advanced verification techniques.