Visibility enhancement for full-chip simulation (intro)

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Home > Journal > September, 2006

Visibility enhancement for full-chip simulation

The article describes how visibility enhancement techniques can be used to gather enough signal value information to debug complex problems without requiring onerous data dumping.

Bio Pic Yu-Chin Hsu is vice president of research and development at Novas Software. He has more than 16 years of R&D experience in EDA, and holds a BSc from Taiwan University, and both MSc and PhD degrees from the University of Illinois.

The most expensive parts of today's system-on-chip (SoC) design flow are where engineers must engage in direct manual effort or expend their energy making decisions. Unfortunately, far too much time and money are wasted on tasks that do not add value — such as trying to figure out if supposedly correct intellectual property (IP) is actually working, debugging 'dumb' errors, or deciding what signals to record in any given simulation run.

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