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Clock domain crossing: guidelines for design and verification success

Clock domain crossing (CDC) errors can cause serious design failures. These can be avoided by following a few critical guidelines and using well-established verification techniques. The guidelines include: When passing 1bit between clock domains:

  • register the signal in the sending clock domain to remove combinational settling; and
  • synchronize the signal into the receiving clock domain. A multi-cycle path (MCP) formulation may be necessary.

When passing multiple control or data signals between clock domains:

  • first attempt to combine multiple signals into a 1bitrepresentation in the sending clock domain before synchronizing the signal into the receiving domain; or
  • use Multi-Cycle Path (MCP) formulations to pass multiple signals across clock domains; or
  • use FIFOs to pass multi-bit buses, either data or control buses; or
  • use gray code counters.

Partition the design sub-blocks into completely synchronous one-clock designs.

Use a clock-based naming convention.

Multi-strategy CDC verification:

  • run a full structural CDC verification at the RTL level;
  • use formal analysis or instrumented simulation to ensure functionality; and
  • re-verify that gates (post-synthesis & scan insertion) still adhere to proper CDC design rules.

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